1. Field of the Invention
The present invention relates to a plasma CVD (Chemical Vapor Deposition) method for forming a thin film, and particularly to a method for forming a low dielectric constant insulation film for a semiconductor device.
2. Description of the Related Art
A plasma CVD film-forming method is a technique of forming a thin film on a substrate in a reaction space by generating plasma by bringing microwaves or RF radio-frequency electric power into a reaction chamber. For methods of bringing electric power in, there are the capacity coupling method, the inductive coupling method, the electromagnetic wave coupling method and others. FIG. 1 shows an embodiment of plasma CVD equipment of a parallel-flat-plate type using a capacity coupling method. By placing two pairs of electrically conductive flat electrodes 101, 102 parallel to and opposing each other within a reaction chamber 104, applying RF power 105 to one side and grounding the other side, the plasma is excited between these two electrodes to form a film on a substrate 103. Radio-frequency electric power in a megahertz band of 13.56 MHz or 27 MHz or in a kilohertz band of 400 kHz is applied independently or by synthesizing them. In addition to this, there are the ICP method, the ECR method using microwaves, helicon wave plasma, and surface wave plasma, etc. In such film-forming equipment, a method in which a plasma source is placed at the top and a substrate on which a film is formed is placed at a lower stage, and the lower stage is electrically grounded or a bias voltage is applied, is widely used.
For methods of forming a low dielectric constant film using the plasma CVD, a method of forming a film using Teflon CFx with a low dielectric constant as a material, a technique which forms a low dielectric constant film by reducing polarizability by adding fluorine to a Si material and other methods have been reported. In the case of techniques using fluorine, however, because device reliability deteriorates due to the corrosiveness of fluorine and low adhesion of the material, these low dielectric constant films of k less than 2.5 have not been put to practical use. When fluorine is not used, to form a low dielectric constant film of k less than 2.5, lowering film density by forming a film porously is required. In conventional plasma CVD methods, however, due to electric phenomena such as a sheath occurring near a wafer caused by the wafer being exposed to plasma and a self-bias occurring at a wafer substrate, a film becomes dense and it is difficult to form a low dielectric constant film of k less than 2.5 or less.
Regarding coating methods, examples of forming a low dielectric constant film of k less than 2.5 or less have been reported including an example of forming a film with a porous structure by controlling sintering conditions and an example of using a supercritical drying method. These methods have not been put to practical use due to many problems, including film quality.
As described above, to integrate semiconductors and to increase the operating speed, in recent years, low dielectric constant films with a dielectric constant of approximately 2.0 are demanded and forming a film with a dielectric constant of approximately 2.0 using a coating method has been reported. However, a film formed by the conventional coating method has problems that it generally has poor film strength and stability and that film formation costs tend to increase. Generally, a thin film formed using a plasma CVD method is of high quality, and thus the method is used in various fields including manufacturing semiconductor devices. An object of the present invention is to form a low dielectric constant film with a porous structure comprising Si materials using a CVD.
One aspect of the invention is a method for forming a thin film on a semiconductor substrate by plasma reaction, comprising the steps of: (i) introducing a reaction gas into a reaction chamber for plasma CVD processing wherein a semiconductor substrate is placed on a lower stage; and (ii) forming a thin film on the substrate by plasma reaction while reducing or discharging an electric charge from the substrate surface. By reducing or discharging an electric charge from the substrate surface, it is possible to prevent nanoparticles generated by plasma reaction from being repelled from the substrate surface, thereby disposing more nanoparticles on the surface.
In the above, in an embodiment, said reducing or discharging is conducted by forming in the reaction chamber upper region for plasma excitation and a lower region for film formation on the substrate wherein substantially no electric potential is applied in the lower region to suppress plasma excitation, thereby reducing an electric charge from the lower region. The above can be achieved when the upper region and the lower region are divided by an electrically conductive intermediate plate having plural pores through which the reaction gas passes, wherein substantially no electric potential is applied between the intermediate plate and the lower stage. Further, when plasma excitation is suppressed in the lower region, nanoparticles do not substantially increase in size. Thus, small nanoparticles can disposed on the surface without interference with an electric charge, so that a film having a fine structure with a low dielectric constant can be obtained.
In another embodiment, said reducing or discharging can be conducted by lowering the temperature of the lower stage to condense moisture molecules present in the reaction chamber on the substrate, thereby discharging an electric charge from the substrate surface.
When the intermediate plate and the lower temperature control of the lower stage are used in combination, more nanoparticles having a small diameter can disposed on the surface.
The present invention can equally be applied to a CVD apparatus for forming a thin film on a semiconductor substrate by plasma reaction. In an embodiment, a CVD apparatus comprises: (a) a reaction chamber; (b) a reaction gas inlet for introducing a reaction gas into the reaction chamber; (c) a lower stage on which a semiconductor substrate is placed in the reaction chamber; (d) an upper electrode for plasma excitation in the reaction chamber; and (e) an electrically conductive intermediate plate with plural pores disposed between the upper electrode and the lower stage, said intermediate plate dividing the interior of the reaction chamber into an upper region and a lower region.
In the above, in an embodiment, the intermediate plate and the lower stage are electrically connected to maintain the intermediate plate and the lower stage at the same voltage. Further, in another embodiment, a CDV apparatus further comprises a temperature controller which controls the temperatures of the lower stage, the intermediate plate, and the upper electrode at xe2x88x9210xc2x0 C. -150xc2x0 C., 50xc2x0 C.-200xc2x0 C., and 100xc2x0 C. -400xc2x0 C., respectively.
The present invention can also be adapted to a film formed by the above-mentioned methods using a gas containing Si (a Si material gas such as an organosilicon and/or non-organosilicon gas), which film is formed with nanoparticles having a particle size of approximately 50 nm or less (preferably approximately 10 nm or less) and has a low dielectric constant of approximately 2.5 or lower (preferably approximately 2.0 or less). The present invention enables forming of a low dielectric constant film using a plasma CVD method. Use of this low dielectric constant film as an insulation film for the next-generation highly integrated semiconductor elements can substantially improve the operating speed of the semiconductor elements by decreasing delays caused by capacity between wiring.
For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
Further aspects, features and advantages of this invention will become apparent from the detailed description of the preferred embodiments which follow.